[LLVMdev] Itineraries in the powerpc backend

[Hal Finkel]

Carter,

In my opinion (and I was the one who committed the changes in question),
it depends on the hardware. The pipeline descriptions are for the PPC
440, which is an embedded PPC chip use in a variety of places. As such,
it is a fairly specific target, and using pipeline-hazard-based
scheduling for specific embedded targets is not uncommon. The backends
for ARM and MBlaze have similar pipeline information for use by their
schedulers.

 -Hal

On Thu, 2011-10-27 at 13:28 -0700, Carter Cheng wrote:
> Hello,
> 
> I was looking over some of the Target commits. I did notice some
> detailed pipeline descriptions in the ppc backends. I havent noticed
> anything in the literature describing this technique. Is this a
> standard approach for mapping SSA to hardware?
> 
> Thanks in advance,
> 
> Carter. 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory