[LLVMdev] Itineraries in the powerpc backend

Hal Finkel hfinkel at anl.gov
Fri Oct 28 02:19:58 PDT 2011


In my opinion (and I was the one who committed the changes in question),
it depends on the hardware. The pipeline descriptions are for the PPC
440, which is an embedded PPC chip use in a variety of places. As such,
it is a fairly specific target, and using pipeline-hazard-based
scheduling for specific embedded targets is not uncommon. The backends
for ARM and MBlaze have similar pipeline information for use by their


On Thu, 2011-10-27 at 13:28 -0700, Carter Cheng wrote:
> Hello,
> I was looking over some of the Target commits. I did notice some
> detailed pipeline descriptions in the ppc backends. I havent noticed
> anything in the literature describing this technique. Is this a
> standard approach for mapping SSA to hardware?
> Thanks in advance,
> Carter. 
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Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory

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