[LLVMdev] Error when cond of select instruction is a vector

Rotem, Nadav nadav.rotem at intel.com
Wed Oct 19 01:21:25 PDT 2011

This is indeed a bug. I get a different error on my machine. Until we solve this bug, as a workaround, you can use the <4 x float> type for which the vselect works.

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Fan Dawei
Sent: Wednesday, October 19, 2011 10:10
To: LLVMdev at cs.uiuc.edu
Subject: [LLVMdev] Error when cond of select instruction is a vector

Hi LLVMdev,

In the specification of llvm ir, the select operation can takes a condition of vector type,
'select' Instruction

  <result> = select selty <cond>, <ty> <val1>, <ty> <val2>             ; yields ty

  selty is either i1 or {<N x i1>}


The 'select' instruction is used to choose one value based on a condition, without branching.

If the condition is a vector of i1, then the value arguments must be vectors of the same size, and the selection is done element by element.

However when I create a program use vector of il as the type of condition. The back-end fails and complains:

SplitVectorOperand Op #0: 0x2b75370: f32 = select 0x2b6c800, 0x2b75270, 0x2b75170 [ID=0]

Do not know how to split this operator's operand!

The following program is a valid IR which passed by the checker. However the back-end fails on all the targets I've tested, including x86, mips and sparc. Is it a target independent bug?

 define void @main() {
  %Cy300 = alloca <4 x float>
  %Cy11a = alloca <2 x float>
  %Cy118 = alloca <2 x float>
  %Cy119 = alloca <2 x float>
  br label %B1

B1:                                               ; preds = %entry
  %0 = load <2 x float>* %Cy119
  %1 = fptosi <2 x float> %0 to <2 x i32>
  %2 = sitofp <2 x i32> %1 to <2 x float>
  %3 = fcmp ogt <2 x float> %0, zeroinitializer
  %4 = fadd <2 x float> %2, <float 1.000000e+00, float 1.000000e+00>
  %5 = select <2 x i1> %3, <2 x float> %4, <2 x float> %2
  %6 = fcmp oeq <2 x float> %2, %0
  %7 = select <2 x i1> %6, <2 x float> %0, <2 x float> %5
  store <2 x float> %7, <2 x float>* %Cy118
  %8 = load <2 x float>* %Cy118
  store <2 x float> %8, <2 x float>* %Cy11a
  ret void

Intel Israel (74) Limited

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