[LLVMdev] Matching addsub

Hal Finkel hfinkel at anl.gov
Mon Oct 17 15:40:29 PDT 2011

How should I go about matching floating-point addsub-like vector
instructions? My first inclination is to write something which matches
build_vector 1.0, -1.0, and then use that in combination with a match on
fadd, but that does not seem to work. I think this is because
BUILD_VECTOR cannot ever be "Legal", and so it is always turned into a
constant load before instruction selection.

Specifically, in SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op):

// A weird case: legalization for BUILD_VECTOR never legalizes the
// operands!
// FIXME: This really sucks... changing it isn't semantically incorrect,
// but it massively pessimizes the code for floating-point BUILD_VECTORs
// because ConstantFP operands get legalized into constant pool loads
// before the BUILD_VECTOR code can see them.  It doesn't usually bite,
// though, because BUILD_VECTORS usually get lowered into other nodes
// which get legalized properly.
SimpleFinishLegalizing = false;

and then:

  switch (TLI.getOperationAction(ISD::BUILD_VECTOR,
Node->getValueType(0))) {
  default: assert(0 && "This action is not supported yet!");
  case TargetLowering::Custom:
    Tmp3 = TLI.LowerOperation(Result, DAG);
    if (Tmp3.getNode()) {
      Result = Tmp3;
  case TargetLowering::Expand:
    Result = ExpandBUILD_VECTOR(Result.getNode());
(so there is not even branch for TargetLowering::Legal). Maybe I'm just
missing something.

Thanks in advance,

Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory

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