[LLVMdev] Enabling Vector-select

Rotem, Nadav nadav.rotem at intel.com
Sun Oct 16 04:09:22 PDT 2011

Hello everyone,

I wanted to let everybody know that I am going to enable the support for vector-select by default later today. 


Currently the LLVM code-generator only supports 'select' [1] instructions with a boolean condition. Vectorizing compilers, such as the Intel OpenCL Vectorizer and the GCC vectorizer often use vector-select instructions to implements masks. This change makes code-generation for these patterns possible.  

In order to enable vector-select we needed to make some changes to the LLVM type-legalizer. 
The '-promote-elements' flag changes the way illegal vectors are legalized. Currently, the default legalization algorithm widens the number of elements in a vector. So, the vector v4i8 would be converted to v16i8. Using the 'promote-element' flag, the legalizer would first try to widen each element. So, the vector v4i8 would be converted to v4i32. Overall this is a good idea because the instruction set is usually more complete for the 'common' element type. This change is required in order to legalize mask types such as '<4 x i1>' into the types which are used by the SSE and Neon instruction sets. 

The X86 backend already has excellent codegen support and it lowers vector-select instructions to SSE4 and AVX blends. Other targets emulate blends using a sequence of ANDs and Xors. 

Later today I will fix a few tests (which expect a slightly different output) and enable the '-promote-element' flag by default. 

[1] http://llvm.org/docs/LangRef.html#i_select
[2] https://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?revision=139992

Intel Israel (74) Limited

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