[LLVMdev] Live code elimination problem in code generation
Jakob Stoklund Olesen
stoklund at 2pi.dk
Fri Oct 14 21:12:21 PDT 2011
On Oct 14, 2011, at 9:04 PM, Hae-woo Park wrote:
> I've met a problem that eliminates a live code in code generation phase.
> The initially generated code is shown as follows (as a pseudo code):
> ( Before pseudo-code expansion. )
> set P0 <- xxx ( P0: a physical register for a parameter of function F )
> set P1 <- yyy ( P1: a physical register for a parameter of function F )
> SELECT_CC z1, z2, z3, ...
> ( <- I don't know why this is scheduled at this time,
> however it is independent from function F )
> call F
> After that, pseudo code expansion stage expands SELECT_CC by slicing the machine basic clock.
I assume you have your own target? I haven't seen this happening with one of the standard targets.
Your analysis is correct, SELECT_CC shouldn't be scheduled there.
Normally, LowerCall will create glue edges between the copyToReg SelectionDAG nodes and the CALL node. Is your target not doing that?
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