[LLVMdev] LLVM and VHDL simulation
Jonas Baggett
jonas.baggett at hefr.ch
Fri Oct 7 09:31:15 PDT 2011
> Does this 'concurrency' mean that we need to figure out
> data-independent instructions in VHDL? Although LLVM-IR is written
> serially, its SSA form explicitly tells us the data dependency between
> temporaries. Then the question is how to map VHDL data types and
> program constructors to LLVM, I think this is not trivial.
>
> I just googled a System C-LLVM tool
> https://forge.imag.fr/plugins/mediawiki/wiki/pinavm/index.php/Main_Page
> which may help?
Thanks for the link. I will look at it.
Suppose we have the following VHDL entity and architecture :
entity Test is
port (A, B, C, D : in Bit;
X, Y, Z : out Bit);
end Test;
architecture Test_RTL of Test is
begin
X <= A And B;
Y <= C And D;
Z <= X Or Y;
end Test_RTL;
The previous block will be synthetized on hardware as a circuit with "AND" and
"OR" gates and without clock because there is only combinatorial logic. The
instructions that calculate X, Y and Z are concurrent so that it is allowed to
put them in any order, although the value of Z depends of the value of X and Y
(to have sequential instructions, a clock must be used).
It is for example allowed to change the order like this :
Z <= X Or Y;
X <= A And B;
Y <= C And D;
because X, Y, and Z are not meant to be calculated sequentially on hardware,
but simultaneously (if we neglect the gate delays) after the change of any of
the inputs. When looking at the equivalent circuit, it is easy to see that no
matter is the order of statements, the synthetized circuit will always be the
same.
To simulate this entity, we will of course execute the instructions sequentially
and Z has to be calculated after X and Y. The order of calculation of X and Y
doesn't matter.
The only difficulty I see with this concurrency is to find a algorithm to
determine the sequence of the instructions to be executed before writing them
to LLVM-IR.
I hope that I answered your question.
Greetings,
Jonas
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