[LLVMdev] Vector-select status update

Rotem, Nadav nadav.rotem at intel.com
Sat Oct 1 04:56:04 PDT 2011


As of recently, the LLVM code-generator started supporting vector-select instructions (select instructions where the predicate operand is a vector of booleans). 

This support includes efficient sequences for targets which have dedicated blend instructions (such as SSE4 and AVX), a slower implementation using
vector AND/OR/XOR instructions for unoptimized targets, and scalarization for targets which do not support vectors. 

For example:  https://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?revision=139992

However, enabling vector-select code generation requires running LLVM with a special flag (-promote-elements), which affects the way 
the LLVM Type-Legalizer legalizes vectors.

This flag is not turned on by default because there are still a few open issues with non-x86 targets (mainly ARM).

If you are interested in having vector-select support then there are a few things that you can do to help:
1. Have a look at pr10902 and try to resolve the last few open issues. 
2. Compile your application using the -promote-elements flag and report any performance regressions (and performance gains!). 

- Nadav

Intel Israel (74) Limited

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