[LLVMdev] x86 backend assembly - mov esp->reg

[Nowicki, Tyler]

Hi,

I've noticed an inconsistency with the x86 backend assembly output in how it treats arguments of a function. Here is a simple test to illustrate the inconsistency:

<from test.c>
void test()
{
  char ac, bc, cc, dc, fc;

  ac = (char)Rand();
  bc = (char)Rand();
  cc = (char)Rand();
  dc = (char)Rand();

  fc = PartialRegisterOperationsTestChar(ac, bc, cc, dc);
}

<from partialregisteroperations.c>
char PartialRegisterOperationsTestChar(char a, char b, char c, char d)
{
  return a*b+c*d;
}

When compiled for atom with clang in 32-bit mode the 8-bit variables in test use 32-bit registers:
       ...
       movl   %ecx, 8(%esp)
       ...
       movl   %ecx, 4(%esp)
       ...
       movl   %ecx, (%esp)
       ...
       movl   %eax, 12(%esp)
       calll  _PartialRegisterOperationsTestChar

However, the 8-bit variables in PartialRegisterOperationsTestChar use 8-bit registers:

_PartialRegisterOperationsTestChar:     # @PartialRegisterOperationsTestChar
# BB#0:                                 # %entry
       movb   16(%esp), %dl
       movb   8(%esp), %al
       mulb   4(%esp)
       movb   %al, %cl
       movb   %dl, %al
       mulb   12(%esp)
       addb   %cl, %al
       movsbl %al, %eax
       ret

I am interested in learning how to change the 8-bit variables in PartialRegisterOperationsTestChar to use 32-bit registers. However, I am new to LLVM and not sure how to do this. I've been trying to find where the mov esp->reg instructions are generated but I haven't had much luck. Could anyone point me in the right direction? Or suggest an another approach for solving this problem?

Comments and suggestions are appreciated,

Tyler Nowicki
Software Developer
Intel Corporation
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