[LLVMdev] LLVM 3.0 release notes ARM Target

[Joe Abbey]

> what do you mean by "more optimal instructions" ?

Could be bad wording... basically, the code generation for the ARM backend keeps getting better and better.

Here's a sample of what I'm talking about:

r144488 | mcrosier | 2011-11-12 21:23:59 -0500 (Sat, 12 Nov 2011) | 10 lines

Add support for emitting both signed- and zero-extend loads.  Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

------------------------------------------------------------------------
r141589 | void | 2011-10-10 18:52:53 -0400 (Mon, 10 Oct 2011) | 18 lines

If the CPSR is defined by a copy, then we don't want to merge it into an IT
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0
------------------------------------------------------------------------
r135017 | evancheng | 2011-07-12 20:42:17 -0400 (Tue, 12 Jul 2011) | 17 lines

Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0
------------------------------------------------------------------------
r133813 | mcrosier | 2011-06-24 15:23:04 -0400 (Fri, 24 Jun 2011) | 23 lines

The Neon VCVT (between floating-point and fixed-point, Advanced SIMD)
instructions can be used to match combinations of multiply/divide and VCVT
(between floating-point and integer, Advanced SIMD).  Basically the VCVT
immediate operand that specifies the number of fraction bits corresponds to a
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3


Joe Abbey
Software Architect
Arxan Technologies, Inc.
1305 Cumberland Ave, Ste 215
West Lafayette, IN 47906
jabbey at arxan.com
www.arxan.com



On Nov 16, 2011, at 9:07 AM, محمد ﻋﻤﺮ ﺩﻫﻠﻮﻯ wrote:

> what do you mean by "more optimal instructions" ?
> 
> -omer
> 
> On Wed, Nov 16, 2011 at 1:28 AM, Joe Abbey <jabbey at arxan.com> wrote:
> I've done a first pass over the past 6 months of changes and some notable things stood out:
> 
>  * The ARM backend has reworked Set Jump Long Jump EH Lowering.
>  * The ARM backend includes improved support for Cortex-M
>  * The ARM backend adds parsing and encoding ARM/Thumb/Thumb2 assembly
> 
> There are also many many code generation improvements which select more optimal instructions.
> 
> Those seemed to be the big items, maybe you know of more and could help Chris with knowing what else is noteworthy for http://llvm.org/docs/ReleaseNotes.html#whatsnew
> 
> Cheers,
> 
> Joe Abbey
> Software Architect
> Arxan Technologies, Inc.
> 1305 Cumberland Ave, Ste 215
> West Lafayette, IN 47906
> jabbey at arxan.com
> www.arxan.com
> 
> 
> 
> 
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