[LLVMdev] alias analysis in ScheduleDagInstr class

[Bjorn De Sutter]

Hi Sergei, thanks for considering my question. We if-convert some code, such that the basic block looks as follows after if-conversion:

ld char from A into R1
p1 = R1>255? (generate the predicate)
p1 |  R1 =  255 (conditional execution)
st char R1 to A
ld char from A+1 into R2
p2 = R2>255? (generate the predicate)
p2 |  R2 =  255 (conditional execution)
store char R2 to A+1

The problem is that the compiler does not seem to know that the second ld can be scheduled before the first st.
 
On 14 Nov 2011, at 16:50, Sergei Larin wrote:

> I am working on something very(very) similar, what is the exact nature of
> your question?
> 
> Sergei Larin
> 
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
> 
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
> Behalf Of Bjorn De Sutter
> Sent: Friday, November 11, 2011 7:59 AM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] alias analysis in ScheduleDagInstr class
> 
> In ScheduleDagInstr.cpp, a todo is mentioned to make this pass use real
> alias analysis information. Is anybody working on this already?
> 
> I am working on a VLIW-like backend and have If-conversion working rather
> well, but the problem is that independent loads and stores in the
> if-converted blocks are not scheduled well at all. 
> 
> Thanks,
> 
> prof. Bjorn De Sutter
> Computer Systems Lab
> Ghent University
> 
> 
> 
> 
> 
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