[LLVMdev] Post increment and register pressure

[Sundeep]

Hi all,

I am analyzing auto inc/dec optimization on ARM. On some loops, I noticed
aggressive post increment is resulting in poor code due to increased
register pressure.

I was wondering if there is a way to estimate register pressure during DAG
Combiner. I am trying to come up with some heuristic based on # of DAG
nodes, # of live ins and live outs, # of machine registers etc. Any
suggestions?

Thanks.

-Sundeep