[LLVMdev] Post-RA scheduler and IssueWidth

[Max Kazakov]

Hi,

Can someone tell me if my understanding is right in that post-RA scheduler
currently assumes no limits on a pipeline's issue width? If so, is it by design
or just overlooked? I have a case for, say, 1-issue pipeline when certain
pipeline resource becomes occupied a few clocks after instruction start, but
hazard evaluation is done incorrectly as scheduler advances clock not for every
(because of 1-issue) cycle but only when resource conflict happens (from its
point of view) within the same cycle. It would be great if someone can help with
explanations on how to make post-RA scheduler to take actual issue rate into
account without modifying current LLVM sources. Otherwise, I have a (trivial)
patch for it.

BR

 m