[LLVMdev] predicates and conditional execution

[Rotem, Nadav]

Hi Roy, 

The LLVM IR does not support predicated instructions. However, it is possible to generate predicated assembly code. The x86 CMov instruction is one example.

I assume that your input program is not predicated and you are trying to use the unique features of your architecture, which has instruction predication.

I can think of several ways to implement this for your backend:

1. You can implement custom lowering to specific operations. The X86TargetLowering::LowerSELECT method in the X86 backend lowers the SELECT instruction to CMOV in many cases.
2. You can implement DAG combining optimizations for your backend which detect interesting patterns.
3. In some cases you can implement codegen patterns (in the td files). I suspect that this will be more difficult to implement and you will have to use #1 or #2.
4. If you are writing a domain specific language, you can generate intrinsic in your LLVM-IR.

Cheers, 
Nadav


-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of roy rosen
Sent: Tuesday, May 24, 2011 10:03
To: llvmdev at cs.uiuc.edu
Subject: [LLVMdev] predicates and conditional execution

Hi,

I was wondering if LLVM supports predicates and conditional execution.
Something like we have in IA64.
There is a register class of predicates and then every instruction may
be predicated by a register from this class.
For example:

cmp_less p, x, y // p is a predicate which gets the result of x < y
p add x, x, 2 // if p then do the add instruction

Is there support in LLVM to something like that?
Which architecture can show a good example for the implementation of that?

Thanks, Roy.
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