[LLVMdev] Possible missed optimization?

Jakob Stoklund Olesen stoklund at 2pi.dk
Sat Mar 26 11:49:14 PDT 2011


On Mar 24, 2011, at 5:42 PM, Borja Ferrer wrote:

> The last copy instruction should be removed as pointed out above, but since R27R26 is killed in the load instruction it has to be emitted. About the insane amount of regclasses there, the load/store and the andi instructions take subsets of regs from the main register class, they cant work with all registers, that's why STW and LDW needs R27R26 since it belongs to the ptr reg class and not R25R24 where the "a" ptr is. As a test i made the load/store instructions work with the DREGS which is the main class and the problem was solved, but of course this is illegal code :)

The coalescer cannot join copies with disjoint register classes.

You need to make sure that there is a register class representing the intersection. Currently, such register classes cannot be inferred automatically by TableGen.

/jakob





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