[LLVMdev] Vector select/compare support in LLVM

[David A. Greene]

Ralf Karrenberg <Chareos at gmx.de> writes:

> Hey,
>
> I am currently forced to create the BLENDVPS intrinsic as an external 
> call (via Intrinsic::x86_sse41_blendvps) which has the following 
> signature (from IntrinsicsX86.td):
>
> def int_x86_sse41_blendvps :
> GCCBuiltin<"__builtin_ia32_blendvps">,
> Intrinsic<[llvm_v4f32_ty],[llvm_v4f32_ty, llvm_v4f32_ty, 
> llvm_v4f32_ty],[IntrNoMem]>
>
> Thus, it expects the mask (first operand if i recall correctly) to be a 
> <4 x float>.
> It would be great to have this mirrored in the IR, meaning one should be 
> able to create a SelectInst with 3 <4 x float> operands which would 
> generate this intrinsic.
> Is there anything that speaks against this?

To me a v4i1 makes more sense as an IR mask type.  The fact that on X86
the native mask type is v4i32 should be handled by the X86 codegen, I
think.

Another option is to rewrite the intrinsic to take a v4i1.  Or more
correctly, create a new intrinsic to live alongside the existing one,
since we want the existing one for gcc compatibility.

                                   -Dave