[LLVMdev] Vector select/compare support in LLVM

[David A. Greene]

"Rotem, Nadav" <nadav.rotem at intel.com> writes:

> One of the arguments for packing masks is that it reduces
> vector-registers pressure.  Auto-vectorizing compilers maintain
> multiple masks for different execution paths (for each loop nesting,
> etc).  Saving masks in xmm registers may result in vector-register
> pressure which will cause spilling of these registers.  I agree with
> you that GP registers are also a precious resource.

GPRs are more precious than vector registers in my experience.  Spilling
a vector register isn't that painful.  Spilling a GPR holding an address
is disastrous.

> In my private branch, I added the [v4i1 .. v64i1] types. I also
> implemented a new type of target lowering: "PACK". This lowering packs

Is PACK in the X86 namespace?  It seems a pretty target-specific thing.

> I also plan to experiment with promoting <4 x i1> to <4 x i32>.  At
> this point I can't really say what needs to be done.  Implementing
> this kind of promotion also requires adding legalization support for
> strange vector types such as <4 x i65>.

How often do we see something like that?  Baby steps, baby steps...  :)

                                -Dave