[LLVMdev] Register class proliferation

[Andrew Trick]

On Jun 21, 2011, at 10:39 PM, Jakob Stoklund Olesen wrote:
> The register allocators will check interference using atoms instead of aliases. That will be faster since every register has fewer atoms than aliases. It also scales well when adding support for register sequence constraints since new super-registers don't add any atoms.
> 
> In the greedy and basic allocators, it means that we will have one LiveIntervalUnion per atom instead of one per physical register as we do it today.

That's one way to make an algorithm scale well--just make the best case expensive enough. Actually, I like this approach very much, I just wonder if we need to 8x liveintervals for pure 64-bit code.

 -Andy