[LLVMdev] [RFC] LegalizeDAG support for targets without subword load/store instructions

Richard Osborne richard at xmos.com
Sat Jul 16 14:01:12 PDT 2011

On 16 Jul 2011, at 03:34, Matt Johnson wrote:

> Hi All,
>     Some targets don't provide subword (e.g., i8 and i16 for a 32-bit 
> machine) load and store instructions, so currently we have to 
> custom-lower Load- and StoreSDNodes in our backends.  For examples, see 
> LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp.  I 
> believe it's possible to support this lowering in a target-agnostic 
> fashion in LegalizeDAG.cpp, similar to what is done for 
> non-naturally-aligned loads and stores using the 
> allowsUnalignedMemoryAccesses() target hook.

The XCore does support i8 and i16 loads and stores. As far as I can remember the standard lowering produced functionally correct code for us. We custom lower misaligned loads and stores because we want to produce code that is better optimized for our target.

In particular if a i32 load is from an address known to be a constant offset away from being word aligned it is quicker to load the two 32bit values at aligned addresses which overlap the data and then shift and or these values to form the result.

Also i32 loads / stores not known to be 32bit or 16bit aligned are expanded to a call to a library function. This can be a big code size win as these operations would otherwise expand to a significant number of instructions.

I'm not sure how this fits in with the changes you want to make. It does sound like the kind of thing that would be good to add to the target independent lowering code,  but I suspect it won't help the XCore backend.



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