[LLVMdev] Post-inc combining

[Bob Wilson]

On Jan 27, 2011, at 11:13 PM, Jonas Paulsson wrote:

> Hi,
> 
> I would like to transform a LLVM function containing a load and an add of the base address inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this
> is exactly what I would like to handle: a simple loop with an address that is inremented in each iteration.
> 
> I am considering using a target intrinsic for this purpose, as the SCEV interface is available on the LLVM I/R. In this way, I could get a DAG with a post-inc-load node instead of the load and add nodes.
> 
> Is this a work in progress? Please explain why these constraints are put in the above mentioned method as they do not seem to facilitate post-inc instruction combining.

The "predecessor" and "successor" terminology used there refers to the DAG, not to the order of the operations in the llvm IR.  For example, if the result of the ADD is the value being stored to memory, then you couldn't fold that into into a post-inc STORE:

 %x = add i32 %addr, 4;
 store i32 %x, i32* %addr

In the DAG for that, the ADD is a predecessor of the STORE.  If the result of the add is used for some other memory reference, then it would not be a predecessor and could be folded.
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