[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms

[David A. Greene]

"Villmow, Micah" <Micah.Villmow at amd.com> writes:

> I have this same problem in our backend. I solve it by adding a pseudo
> instruction at instruction selection that transforms @R1 into R1, so
> only a single pattern is required. I then can propogate the pseudo
> instruction after instruction selection.

What's the rationale behind this approach?  It seems a bit clumsy to me.
An instruction with varying addressing modes is not a single
instruction.  They have different encodings, for starters.  Defining
separate patterns for them is the "clean" LLVM approach.  I would think
your approach adds the danger of the pseudo-instruction getting lost at
some point.

If the redundancy in specifying patterns for different addressing modes
is the problem, I have some stuff to submit that helps with that.  It
will probably take quite a bit of patch churn before it makes it to
trunk, however.

                               -Dave