[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms

[Villmow, Micah]

I have this same problem in our backend. I solve it by adding a pseudo instruction at instruction selection that transforms @R1 into R1, so only a single pattern is required. I then can propogate the pseudo instruction after instruction selection.

Micah

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Lu Mitnick
Sent: Tuesday, January 18, 2011 10:29 AM
To: llvmdev at cs.uiuc.edu
Subject: [LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms

Hello all,

I am at the adding Instruction Set stage of adding new target support into LLVM. There is a single instruction op mnemonic with multiple operand forms. For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the solution of x86 is adding suffix of instruction and translating instruction op mnemonic into ADDrr & ADDmr. I don't want to translate single instruction op mnemonic with different operand forms into multiple op mnemonics. I am wondering to know whether is another solution of this problem or not?? Which target should I look for it??

thanks a lot

yi-hong
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