[LLVMdev] Support Target with no register,register operations

[Steve Montgomery]

I'm writing a back-end for a target in which all dyadic instructions support one register and one memory operand but only some instructions support two register operations. For example ADDrm and ADDrr are supported, ANDrm is supported but ANDrr isn't.

I've written descriptions for ADDrm, ADDrr and ANDrm in my InstrInfo.td file but instruction selection fails when presented with an AND that has two register operands, e.g.

e = (a + b) & (c + d);

I guess I need to force one of the operands of the AND operator into a stack slot but as I'm pretty new to LLVM I'm not sure which phase to do this in. Could anyone offer some suggestions as to the best way to handle this kind of target?