[LLVMdev] Instructions with register constraints

Damien Vincent damien.llvm at gmail.com
Fri Apr 8 10:13:06 PDT 2011

 For any instruction, a list of constraints can be specified, like:
let Constraints = "$dst = $lhs" in

 I checked the existing backends and I didn't notice any complex
constraints: basically "Constraints" keyword is used to force 1 operand
register to be the same as  another one.
I am wondering if there is any way to express more complicated constraints
like for example:
- if $lhs is either r0,r1,r2,r3 then $dst should also be in the set
- if $lhs is either r4,r5,r6,r7 then $dst should also be in the set {r4, r5,
r6, r7}

  Thank you !

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110408/8e8d3ac7/attachment.html>

More information about the llvm-dev mailing list