[LLVMdev] GSoC 2011: Fast JIT Code Generation for x86-64

Viktor Pavlu vpavlu at gmail.com
Wed Apr 6 07:47:29 PDT 2011

Thanks for all the replies!

I wanted to closely resemble what the CACAO VM[1] backend did with
success for a long time: for every CACAO IR instruction, there is a
sequence of x86 instructions that get written directly to the executable
memory. In CACAO, registers are used while available, then everything is
spilled. Relocations are resolved and patched in a second go.

It seems this is similar to what Tilmann refers to in the old qemu JIT:

On Tue, Apr 5, 2011 at 11:49 PM, Tilmann Scheller
<tilmann.scheller at googlemail.com> wrote:

> The old qemu JIT used an extremely simple and fast approach which performed
> surprisingly well: Having chunks of precompiled machine code (from C
> sources) for the individual IR instructions which at runtime get glued
> together and patched as necessary.

> The idea would be to use the same approach to generate machine code from
> LLVM IR, e.g. having chunks of LLVM MC instructions for the individual LLVM
> IR instructions (ideally describing the mapping with TableGen), glueing them
> together doing no dynamic register allocation, no scheduling.

> I'd be willing to mentor such a project, let me know if you're interested.

So yes, I would be interested.

Only recently is CACAO starting to get a register allocator to improve
quality of the generated code.
I wanted to include this in my first stab at the project but leaving
register allocation for future work or even for the regular backend is
fine with me, too.

- Viktor


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