[LLVMdev] [LLVMDev] [Modeling] About the structure of my allocator

[Jeff Kunkel]

Perhaps what I think is a problem really is not a problem.

So when a jump occurs from one block A to block B, then the registers are
certain state, and register allocation happens with the initial state
defined by A->B. When a third block C jumps to block B, the state of the
registers are different. Thus register allocation needs to account for the
jump from C->B, by a few ways:

1. The allocator defines A->B as the conformity state. Thus when C->B, C
must conform to the state of the register from A.
2. A branch may occur where B' = B in respect to the instructions, but
register allocation from C->B' will be different because of differing
initial states.

The information I need is where the jumps occurs in the instructions
vector.

Thanks,
Jeff Kunkel


On Thu, Sep 2, 2010 at 8:05 PM, Dale Johannesen <dalej at apple.com> wrote:

> It is at the end allowing for oddities like debug info and multiple
> branches.  You might want to look at AnalyzeBranch.
>
> On Sep 2, 2010, at 4:19 PMPDT, Jeff Kunkel wrote:
>
> Is there any way to tell where in the Instruction list, the branch to the
> other MachineBasicBlock happens? I know in the BasicBlock had a nice api for
> it.
>
> Thanks,
> Jeff Kunkel
>
> On Thu, Sep 2, 2010 at 5:56 PM, Dale Johannesen <dalej at apple.com> wrote:
>
>>
>> On Sep 2, 2010, at 2:44 PMPDT, Jeff Kunkel wrote:
>>
>>> I need to track which MachineBasicBlocks branch into other
>>> MachineBasicBlocks. How do I do it?
>>>
>>
>> Look at the Predecessor/Successor lists, which are target-independent
>>
>>
>>  I see a MachineOperand can hold a MachineBasicBlock*. Does this mean the
>>> instruction may branch to the MachineBasicBlock, or can it be something like
>>> an object reference?
>>>
>>
>> It can also be the dreaded gcc "address of label" extension.  Number and
>> ordering of instruction operands is target-dependent.
>>
>>
>>
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