[LLVMdev] Invoking LLVM front-end

[ether zhhb]

hi,

I have done something like this,  i am focusing translating LLVM IR to
Verilog HDL, but not care about C/C++ source code at this moment.

I implement this as a llvm backend as Kunkel said.

At the current state, i write my own schedule DAGNode classes, which
allow me to schedule multiple Nodes to the same cycle, perform
resource binding and register allocation.

And i am planning to implement a generic LLVM target machine, so i can
and first translate LLVM IR to LLVM machine code, to leverage existing
low level llvm optimizations. and then i will translate these LLVM
machine code to my own schedule DAGNodes.

and you could also have a look at this: http://legup.org/, this is a
open source high level synthesis project(not my project).

best regards
ether

On Tue, Oct 12, 2010 at 6:19 AM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> I forgot to cc the list
>
> On Mon, Oct 11, 2010 at 6:19 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
>> Well this is my 20,000 foot viewpoint of the project you have
>> described. Also, I would appreciate if someone more knowledgeable
>> revised my statements.
>>
>> First, I would make a mock machine with large register banks for each
>> kind of operation and size combination. The large register bank will
>> fool the upper levels because the upper levels only look at register
>> pressure and register classes. Since supposedly, you do not want to
>> restrict the compiled code into a machine, but instead you wish to
>> create the machine.
>>
>> Second, I would rewrite the whole CodeGen piece of the code because
>> SSA form goes into the CodeGen and machine code comes out. Since the
>> kind of optimizations the current independent code generator does is
>> restricting the SSA form into a certain machine; this does not
>> correlate with the goals of your project. While some operations may be
>> useful from the codegen like instruction scheduling and instruction
>> lowering, you wish to dynamically define which operations to combine
>> before lowering. If there are many add followed by a shift, then you
>> wish to create the instruction add-shift on the fly. Since, you do not
>> know the instructions before hand, you may optimize them accordingly.
>>
>> From that part onwards, you would have complete control of the code.
>>
>> As for not being a pass, well yes and no. You can certainly write your
>> code as passes into the CodeGen. You may create custom headers with
>> your data structures and format your code accordingly, or you may just
>> hook into the first and only code gen pass for you mock machine.
>>
>> My 2 cents,
>> Jeff Kunkel
>>
>>
>>
>> On Mon, Oct 11, 2010 at 5:42 PM, Taemin Kim <taemin0712 at gmail.com> wrote:
>>> Hello LLVMers,
>>>
>>> I am developing hardware generation tool which converts C/C++ application to
>>> hardware which is not a Pass but a separate project. I am going to use LLVM
>>> as front-end optimization tool. I am curious how I can invoke the LLVM
>>> front-end optimziations and then, get the pointer of LLVM IR data generated
>>> by the front-end. I would like to perform some optimziations on the IR. Can
>>> anybody please direct me to some example codes or documentation about that?
>>>
>>> Thank you.
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>
>>>
>>
>
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