[LLVMdev] register constraints

[Bob Wilson]

On Oct 8, 2010, at 5:21 AM, Jonas Paulsson wrote:

> Hi,
> 
> I have worked with GCC prior to using LLVM, and I am a bit startled to find no way to use an earlier operand as is done in GCC.
> 
> For example, a sext instruction on my target takes one the operand of a low-part register, and then sign extends into the full register.I find that there is no way to use for example (set RC:$srsc, sext($src, 16)), or in any other way use a sext operator to perform this on one register.

LLVM keeps the IR in SSA form until just before register allocation.  You can't have an instruction like that in SSA because $src would have multiple definitions.  Instead, you can add a constraint to the instruction definition, something like "$dst = $src", to indicate that both operands must be allocated to the same register.  The TwoAddressInstructionPass will then make sure that happens.

> It would be neat to be able to do this somehow. When I define a sext_inreg instruction, LLVM does not match the sext node in the DAG with this, unfortunately.

This might be a different problem.  I suspect you're confusing the sext and sext_inreg operations.

If the type that you are extending from, e.g., 16-bit integer, is not a legal type for your target, then before selection DAG matching all the 16-bit values will be legalized to some legal types, e.g., 32-bit integers.  At that point a "sext" (e.g., 16 to 32 bits) may turn into a "sext_inreg" (e.g., source operand is already 32 bits but the high bits need to be set).

Those are just a few things to get you started on the right track.  I hope it helps.

> 
> How is feats like this supposed to be done? Right now it seems that I need to do a custom lowering impelementation to replace the sext-SDValue with a subgraph with a 32bit virtual register, a copy to the low subregister, and then a sext_inreg node. Am I right?
> 
> I would appreciate any answer,
> 
> Jonas
> 
> 
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