[LLVMdev] Creating tablegen patterns for intrinsics with no return value.

[Villmow, Micah]

I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted.

Here is my profile/node/pattern.
Profile:
def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [
    SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
    ]>;
Node:
def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;

Pattern:
def ATOM_G_ADD_NORET     : BinAtomNoRet<IL_OP_UAV_ADD,
      "_id($id)", atom_g_add_noret>;


I am Lowering INTRINSIC_W_CHAIN to lower from @llvm.amdil.atomic.add.gi32.noret to the correct instruction with the following code sequence.

LowerINTRINSIC_W_CHAIN(...)
{
...
case AMDILIntrinsic::AMDIL_atomic_add_gu32_noret:
             IntNo = AMDILISD::ATOM_G_ADD_NORET; break;
...
  SDValue Ops[6];
  SDValue chain = Op.getOperand(0);
  unsigned numNodes = 0;
  if (inChain) {
    Ops[numNodes++] = chain;
  }
  SDValue Chain = Op.getOperand(0);
  Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1);
  Ops[numNodes++] = DAG.getConstant(1, MVT::i32);
  Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32);
  Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes);
  if (outChain) {
    SDValue mv[2] = {Op, chain};
    Op = DAG.getMergeValues(mv, 2, dl);
  }
  return Op;
}

I'm guessing I am not handling the chain correctly, but I'm not sure what I am doing wrong. Can someone point me to an example of matching an intrinsic to a machine instruction with no return value?

Thanks,
Micah
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