[LLVMdev] backend question

[Jakob Stoklund Olesen]

On May 25, 2010, at 8:19 AM, Lev Yudalevich wrote:

> Hello,
> 
> I'm just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of register rs to register rd and places the result in rd; add.cc rd, rs does the same and updates the condition codes. Can anybody point out an example of how such instructions should be defined in a corresponding xxInstrInfo.td file please?

ARM has similar instruction pairs, look at ADD/ADDS, SUB/SUBS in ARMInstrInfo.td

/jakob