[LLVMdev] how to lower MUL i64 for soft int arithmetic?

[Sergey Yakoushkin]

Dear, SelectionDAG developers, could you please comment on this issue
and clarify internals of MUL lowering?

Does my case (processor with soft MUL) supported by current design or
such architectures are out of scope? How lowering of large MUL is
supposed to work? What kind of minimalistic support should be provided
by target back-end? What can be used from current LegalizeDAG?

- Thanks, Sergey

2010/3/18 Sergey Yakoushkin <sergey.yakoushkin at gmail.com>:
> Hi,
>
> LLVM mis-compiles soft int64 mul '__muldi3' (either libgcc or
> compiler-rt) unless some specific efforts are taken in the back-end to
> custom lower i64 operations back to i32.
>
> Issue appears also in CellSPU/Alpha, and there exist workarounds which
> use custom lowering to vector instructions.
>
> My case is different.
>
> Deeply embedded processors have optional multiplier unit (e.g.
> disabled at design time). Thus, efficient and compact MUL
> implementation is not available, i32 mul is implemented as __mulsi3 in
> libgcc.
>
> Seems retargetable back-end requires additional efforts in this case:
> either to rewrite __muldi3 source code to avoid mul promotion or to
> custom lower i64 mul.
>
> Am I missing someting?
>
> Does this problem affects existing back-ends like PIC16?
>
> Could you please help with some hints. How to implement mul i64
> lowering to mul i32 (which must be replaced with __mulsi3)? are there
> any examples in existing back-ends?