[LLVMdev] thinking about timing-test-driven scheduler

Kalle.Raiskila at nokia.com Kalle.Raiskila at nokia.com
Fri Jun 11 07:17:05 PDT 2010

On Wed, 2010-06-09 at 17:30 +0200, orthochronous wrote:
> Hi,
> I've been thinking about how to implement a framework for attempting
> instruction scheduling of small blocks of code by using (GA/simulated
> annealing/etc) controlled timing-test-evaluations of various
> orderings. 

This sounds interesting. 

> (I'm particularly interested small-ish numerical inner loop
> code in low-power CPUs like Atom and various ARMs where there CPU
> doesn't have the ability to "massage" the compiler's scheduling.)

Have you tried to do some benchmarking here? E.g. high-end x86 vs. Atom
processors? Does the current scheduler do a bad job here?

> Are there any
> obvious reasons why this is actually a bad approach to the problem? On
> the assumption that its a reasonable idea, it involves repeatedly
> calling reg-alloc and machine code execution from an unexpected point
> in the llvm system, 

This sort of framework would be nice to have also for (especially for)
processors that one must cross compile for (or don't have JIT). 
Just a thought...


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