[LLVMdev] Spilling multi-word virtual registers

Ken Dyck Ken.Dyck at onsemi.com
Tue Jul 20 10:57:50 PDT 2010

Does anybody have any tips for generating spills/reloads for large
non-vector registers?

I'm working on a back end for a DSP architecture that has accumulator
registers that are too large to be spilled or reloaded with a single
instruction. All of their bits can be accessed in word-size chunks via
three sub-registers (low, high, and ext). So loading or storing one
requires three instructions: one for each sub-register.
For quite a while now, my implementation of loadRegFromStackSlot() and
storeRegToStackSlot() has assumed that it would only receive physical
registers, which makes it fairly straight-forward. They generate three
memory instructions, calling TargetRegisterInfo::getSubReg() to get the
sub-register operand for each of them.

So it was a rude awakening when a test program resulted in a _virtual_
register being passed into loadRegFromStackSlot() (via
LiveIntervals::tryFoldMemoryOperand() if it matters). Obviously I need
to make some changes. But what?

A couple options immediately come to mind:

1. Generate INSERT_SUBREG/EXTRACT_SUBREG machine instructions in
loadRegFromStackSlot() and storeRegToStackSlot() to handle virtual
registers. Will this work? Is it safe to create additional virtual
register from these methods?

2. Emit a single pseudo-instruction for large loads and stores and use a
custom pass to expand it to multiple instructions after register

Any other suggestions?


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