[LLVMdev] Question on the use of TableGen

[Dongrui She]

Hi all,

I'm trying to create a new backend for a processor, and I start with
modifying the existing backends like MIPS and Microblaze.

I have a problem when I try to add a register class in the Target's register
description, it looks like this:
def IGPRegs : RegisterClass<"MBlaze", [v8i16], 128, [PR0, PR1,  PR2,  PR3]>;
// PR0 - PR3 are registers defined before

I want to have a new integer register file for a different type, e.g. v8i16.
But then I got errors when running tblgen.

Here is the error I  got when modifying the MBlaze backend:

BSLLI:     (set CPURegs:i32:$dst, (shl:i32 CPURegs:i32:$b,
(imm:{i32:v8i16})<<P:Predicate_immZExt5>>:$c))
../../../bin/tblgen: error:
Included from .../llvm/lib/Target/MBlaze/MBlaze.td:25:
.../llvm/lib/Target/MBlaze/MBlazeInstrInfo.td:347:5: error: In BSLLI: Could
not infer all types in pattern!
    def BSLLI  :  ArithI<0x11, "bslli  ", shl, uimm5, immZExt5>;
    ^

It seems that defining a new register class changes how the tblgen infers
the types in the DAG patterns.
So what is the right way to add a register class for a different type?


-- 

Regards,

Dongrui
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