[LLVMdev] Register Spilling and SSA
dag at cray.com
Mon Jan 18 08:57:33 PST 2010
On Sunday 17 January 2010 07:00, Mark Muir wrote:
> Those counts simply don't mean anything in the real world.
> This certainly is the case with desktop CPUs, where the hardware designers
> have gone to a lot of bother adding hardware to perform dynamic
> rescheduling and register renaming, which effectively replace these stack
> accesses with registers or access to fast cache.
> But, with upcoming architectures - particularly ones with a very large
> number of cores (e.g. something along the lines of Larrabee, or Ambric,
> and a plethora of others) - such hardware is too costly. As a result,
> needless stack activity consumes available memory bandwidth, which
> absolutely hammers instruction-level parallelism.
Granted, "anything" is a bit strong. But I stand by the idea that measuring
spills isn't telling the real story. The real story often has more to do with
*what* is spilled rather than how much is spilled. I believe that is true on
in-order machines as well.
It's true that instruction count generally tracks performance. But when
trying to eke out the last bit of speedup, simple counts simply aren't enough.
Changing a register allocator is a rather drastic thing to do, so I want to
see how it really impacts performance.
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