[LLVMdev] TableGen !eq() Operator Patch
dag at cray.com
Tue Jan 5 09:59:16 PST 2010
Attached is a patch to implement an !eq() operator in TableGen. We use this
for the AVX specification to allow the user to control what kind of pattern
should be used for a particular instruction def. For example, we use it for
reg-mem instructions to let the user choose between a built-in generic reg-mem
pattern, the same pattern that was used for the reg-reg variant of the
instruction or a custom pattern provided by the user.
It only operates on strings.
An alternative to this would be to implement named parameters in TableGen but
that seems like overkill for this case. Named parameters could be useful in
other areas to reduce template complexity but implementing it is non-trivial
given the widespread assumption in the TableGen sources that template
parameters exactly match up with template arguments.
Comments? Ok to commit?
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