[LLVMdev] ASM output with JIT / codegen barriers
resistor at mac.com
Mon Jan 4 01:32:30 PST 2010
On Jan 4, 2010, at 1:17 AM, Chandler Carruth wrote:
> Side note: I regret greatly that I didn't know enough of the
> sequential consistency concerns here to address them more fully when I
> was working on this. =/ Even explicit fencing has subtle problems with
> it as currently specified. Is this causing problems for people (other
> than jyasskin who clued me in on the whole matter)?
Talking about memory consistency is always painful. In particular, there's a disconnect between how consistency models think about reorderings, versus how the compiler and hardware actually perform them.
There's a natural tension between sanity (make all atomic ops sequentially consistent) and performance (no consistency by default, frontend must supply it via fences). So far we've been pursuing the latter approach: C-level atomic intrinsics are emitted as fence-atomicop-fence. The X86 backend then has some knowledge (thanks to X86's comparatively strong memory model) of instances where fences can be folded away.
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