[LLVMdev] Paired register allocation problem
pietreka at gmail.com
Mon Feb 22 07:39:34 PST 2010
Thanks for reply
> I have defined registers, aliases and subregister set.
> > The problem is that register allocator is using 32bit registers that are
> > already used in a pair, for example:
> > lw $r0, 16[$r12] // load word to r0
> > ld $p0, 36[$r12] // load doubleword to p0
> > shl $p0, $p0, $r0 // shift left p0 by r0 and store result in p0
> > where p0 is a pair r0:r1
> > Could anyone tell me what am I doing wrong?
> Have you defined aliases properly? Look how this is handled inside
> s390 backend (systemz).
I've compared again everything to systemz. The problem was I've defined
paired class as a subclass of Register class instead of RegisterWithSubRegs
class. After change the code is OK.
> Note that in general you'll need to write "paired" reg-reg mov pseudo
Yes, I have those.
If you don't mind I'll ask few compilers/LLVM newbie questions.
I'd appreciate if someone could enlighten me on pseudo instructions.
These work fine if I want to print assembly. What if I want to generate a
binary file directly: how can I expand something like this:
mov $p0, $p1
into two instructions:
mov $r0, $r2
mov $r1, $r3
Another problem: All of my instructions which operates on 64bit operands,
take pairs of 32bit registers. However in some of these instructions
registers are encoded as a pair number and in some as two single register
numbers for each pair.
Similar problem with immediates which not fit in 10bits - they are encoded
as separate upper22 bits and lower10 bits (64 bits long version of
instruction instead of 32 bits).
Thanks a lot for explanation/suggestions
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