[LLVMdev] Master's thesis: Retargetable Compiler Backend for Transport Triggered Architectures
pekka.jaaskelainen at tut.fi
Thu Feb 18 04:25:56 PST 2010
I think this master's thesis from our group could be of
interest. It describes the "bridge" between the LLVM codegen
and our custom TTA codegen in TCE: a runtime retargetable architecture
description file driven LLVM compiler backend. The thesis might be
useful also for people implementing backends for LLVM in general.
If you have any questions or comments, please direct them to
me (I'm not the author of this thesis despite my almost identical
name) as the author is no longer working for our department.
The abstract from the thesis:
Embedded computer systems can be found everywhere as the result of the
need to develop ever more intelligent and complex electronic devices.
To meet requirements for factors such as power consumpiton and performance
these systems often require customized processors which are optimized for
a specific application. However, designing an application specific processor
can be time-consuming and costly, and therefore the toolset used for processor
design has an important role.
TTA Codesign Environment (TCE) is a semi-automated toolset developed at the
Tampere University of Technology for designing processors based on an easily
customizable Transport Triggered Architecture (TTA) processor architecture
template. The toolset provides a complete co-design toolchain from
program source code to synthesizable hardware design and program binaries.
One of the most important tools in the toolchain is the compiler. The compiler
is required to adapt to customized target architectures and to utilize the
available processor resources as efficiently as possible and still produce
programs with correct behavior. The compiler is therefore the most complicated
and challenging tool to design in the toolset.
The work completed for this thesis consists of the design, implementation and
verification of a retargetable compiler backend for the TCE project. This
thesis describes the role of the compiler in the toolchain and presents the
design of the implemented compiler backend. In addition, the methods and
benchmark results of the compiler verification are presented.
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