[LLVMdev] Integrated instruction scheduling/register allocation
evan.cheng at apple.com
Sat Feb 6 01:23:07 PST 2010
On Feb 5, 2010, at 2:01 AM, Gergö Barany wrote:
> On Thu, Feb 04, 2010 at 13:59:08 -0800, Evan Cheng wrote:
>> A more pressing need is a pre-regalloc scheduler that can switch modes to
>> balance reducing latency vs. reducing register pressure.
> Right. I'm actually working on implementing a variant of IPS (Goodman and
> Hsu, Code scheduling and register allocation in large basic blocks,
> http://doi.acm.org/10.1145/55364.55407) based on the existing list-td and
Well, David is a LLVM contributor himself so perhaps he can give you some pointers.
> list-tdrr schedulers; this requires handling of physical register
> dependencies in those schedulers, which I am currently struggling with. It's
> all in a very messy pre-prototype stage, but I'm getting there and will be
> happy to contribute my work when it's nice and clean.
Sounds great. Thanks.
> Thanks for the feedback, Jakob and Evan.
> Gergö Barany, research assistant gergo at complang.tuwien.ac.at
> Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/
> Vienna University of Technology Tel: +43-1-58801-58522
> Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598
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