[LLVMdev] Register design decision for backend
Jakob Stoklund Olesen
stoklund at 2pi.dk
Tue Aug 31 16:55:49 PDT 2010
On Aug 31, 2010, at 1:06 PM, Borja Ferrer wrote:
> Incase i wasnt clear enough i'll expose a simple example using the common known x86 arch.
> AX is composed by AL and AH (AX and AH are subregs of AX), now assume x86 can only add regs of 8 bits, so if a i16 number is stored in AX it should get splitted into AL and AH so that the 8 bit addition pattern is matched.
> If this is what you meant from a start sorry for the noise, since that wasnt clear to me. Adding that transform to your reg allocator would be great since i cant continue writing the backend until this issue is resolved. I think this case should be handled by all register allocators implemented in LLVM, so maybe it can be factored out before using an specific allocation algorithm.
The LLVM target descriptions don't model sub registers well enough to do this. The target-independent code generator only knows that EAX has sub registers AX, AH, and AL. It does not know the positions of the sub registers in the super registers, or that EAX has bits that are not covered by sub registers.
The transformations you are looking for should be done on the selection DAG. Look at how the other targets are using setOperationAction() in their TargetLowering.cpp files.
> I have noticed that some changes have been done in all registerinfo.td backend files concerning subreg classes and indices since v2.7, do these changes fix this problem or they didnt have any functional changes?
No, those changes were to simplify the specification of complicated register banks, like the ARM NEON registers.
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