[LLVMdev] global type legalization?
bob.wilson at apple.com
Wed Aug 18 10:59:09 PDT 2010
On Aug 18, 2010, at 10:42 AM, Chris Lattner wrote:
> On Aug 18, 2010, at 10:27 AM, Bob Wilson wrote:
>>> I tend to think that it isn't worth the compile time to try to microoptimize out every compare, but I could be convinced otherwise if there are important use cases we're failing to handle. I also do think that whole-function selection dags will solve a lot of grossness (e.g. much of codegen prepare) with a very clean model.
>> I'll take a look at Machine CSE and Machine Sink. Where is the heuristic for tracking live-out vregs that you mention? I'm definitely seeing a reextend of an already extended value. Worse, the value is spilled and the zext is not folded into the reload.
> The code I'm thinking of is in SelectionDAGISel::ComputeLiveOutVRegInfo
I will check it out. Thanks!
>> For ARM and possibly other RISC-like targets, you simply can't define an i8 or i16 value -- those aren't legal types. Since those values will always be extended at the point where they are defined, the code placement problem is straightforward: you always want to fold the extends into the def, as long as the value is always extended the same way (not mixed sign and zero extends). Whole function selection DAGs would make that easy.
> Right. This is a bit trickier than you make it sound though, because an "i8" addition isn't neccessarily zero or sign extended when the add is done in a 32-bit register.
Oh right. I was oversimplifying. So, you do NOT always want to fold the extends into the def. E.G., if the only use is a store-byte, you wouldn't want to add a separate extend instruction after an i8 add. That really makes whole-function selection DAGs sound like the right solution.
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