[LLVMdev] Upstream PTX backend that uses target independent code generator if possible
Micah.Villmow at amd.com
Tue Aug 10 12:25:42 PDT 2010
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of David A. Greene
> Sent: Tuesday, August 10, 2010 12:02 PM
> To: Che-Liang Chiou
> Cc: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Upstream PTX backend that uses target
> independent code generator if possible
> Che-Liang Chiou <clchiou at gmail.com> writes:
> > I surfed their code, and it seems that they didn't use code
> > That means there design should be similar to CBackend or CPPBackend.
> > So I guess it can't generate some machine instructions like MAD,
> > and there are some PTX instruction set features that are hard to
> > if not using code generator.
> > But I didn't study their code thoroughly, so I might be wrong about
> I haven't had a chance to look at it yet either.
> >>> I have tested this backend to translate a work-efficient parallel
> >>> kernel (
> >>> ) into PTX code. The generated PTX code was then executed on real
> >>> hardware, and the result is correct.
> >> How much of the LLVM IR does this support? What's missing?
> > Have to add some intrinsics, calling conventions, and address spaces.
> > I would say these are relatively small changes.
> Are you generating masks at all? If so, how are you doing that?
> Similarly to how the ARM backend does predicates (handling all the
> representation, etc. in the target-specific codegen)?
> I've have been wanting to see predicates (vector and scalar) in the
> LLVM IR for a long time. Perhaps the PTX backend is an opportunity
> to explore that.
[Villmow, Micah] From looking at the llvmptxbackend, it does not fully support vector types.
This in my perspective is one of the greatest benefits of the backend code-generator, automatic support
for vector types in LLVM-IR that are not natively supported by the target machine via vector splitting.
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