[LLVMdev] indirectbr and phi instructions

[Bill Wendling]

On Aug 2, 2010, at 3:19 PM, Joshua Warner wrote:

> Hi,
> 
> How does the requirement that phi instructions have one value per predecessor basic block interact with indirectbr instructions?  For instance, take the following code:
> 
> L1:
>    br i1 %somevalue, label %L2, label %L3
> L2:
>    %ret1 = i8* blockaddress(@myfunction, %L5)
>    br label %L4
> L3:
>    %ret2 = i8* blockaddress(@myfunction, %L6)
>    br label %L4
> L4:
>    %ret = phi i8* [%ret1, L2], [%ret2, L3]
>    indirectbr i8* %ret, [label %L5, label %L6]
> L5:
>    %myval = phi i32 [0, %L2], [1, %L3] ; are both of these values required, even though the only *real* possible predecessor block is L2?
>    ret i32 %myval
> L6:
>    %myval = phi i32 [0, %L2], [1, %L3] ; likewise
>    ret i32 %myval
> 
> Boiled down, I think my question is, "how strict is the 'one value per predecessor block' rule on a phi instruction?"
> 
Actually, if you look at your example, it will fail because of the PHIs in L5 and L6. :-) The PHI node entries must match up one-to-one and onto with the predecessors. Here's an example that will fail during code-gen:

@a1 = global i8* blockaddress(@foo, %bb4)
@a2 = global i8* blockaddress(@foo, %bb5)

define i32 @foo(i1 %a, i32 %b) {
entry:
  %a1_ = load i8** @a1
  %a2_ = load i8** @a2
  br i1 %a, label %bb1, label %bb2

bb1:
  %v1 = add i32 %b, 37
  br label %bb3

bb2:
  %v2 = add i32 %b, 927
  br label %bb3

bb3:
  %addr = phi i8* [%a1_, %bb1], [%a2_, %bb2]
  indirectbr i8* %addr, [label %bb4, label %bb5]

bb4:
  %v_bb4 = phi i32 [%v1, %bb1], [%v2, %bb2]
  br label %exit

bb5:
  %v_bb5 = phi i32 [%v1, %bb1], [%v2, %bb2]
  br label %exit

exit:
  %p = phi i32 [%v_bb4, %bb4], [%v_bb5, %bb5]
  ret i32 %p
}


-bw