[LLVMdev] request for help writing a register allocator

[Chris Lattner]

On Oct 20, 2009, at 7:22 AM, Susan Horwitz wrote:

> On Mon, 19 Oct 2009, Chris Lattner wrote:
>
>> Other advice: if you're looking to simplify this for students, I'd  
>> recommend staying away from X86 or ARM, which use subregs heavily.   
>> If you work with (e.g.) the sparc backend, you can avoid them  
>> completely, simplifying the problem.
>
> Chris -
>
> Thanks for your reply!  But I'm confused about the above.  In  
> particular, another reply said the following:
>
>> For each virtual register the  
>> MachineRegisterInfo::getRegClass(<vreg>) method will give you a  
>> TargetRegisterClass. You can use the allocation_order_begin/ 
>> allocation_order_end methods to iterate over the allocable physregs  
>> in that class.
>
> If I can get the appropriate physical register for each virtual one  
> this way, then how does X86's use of sub-registers complicate my  
> register-allocation code?

Each virtual register has an assigned register class.  However,  
register classes relate to each other, and the machine IR also has  
subreg references.  For example, this is how X86 handles AL/AX/EAX/RAX  
all aliasing each other.  In the Sparc backend, the only aliases are  
in the FPU, and it doesn't use subregs to model them at this point.

-Chris