[LLVMdev] RFC: AVX Feature Specification
dag at cray.com
Wed May 27 14:20:04 PDT 2009
On Wednesday 27 May 2009 13:58, Stefanus Du Toit wrote:
> On 30-Apr-09, at 6:38 PM, Dan Gohman wrote:
> > On Apr 30, 2009, at 3:02 PM, David Greene wrote:
> >> As I've been going along I've added feature flags for SSE4a and
> >> SSE5. These
> >> really do need to be separate feature flags because having SSE4a and/
> >> or SSE5
> >> does not imply that you have SSE4.2 or SSE4.1. So they can't be
> >> part of the
> >> X86SSELevel scheme.
> > Offhand, I'd say SSE4a and SSE5 ought to be separate flags too.
> FWIW we added a flag for SSE4A in a commit yesterday, as well as more
> AMD architecture types.
Cool. I'm about ready to start committing some meaty stuff. I'm out of town
the rest of the week but there should be a flurry of things next week.
I've got pretty far in the AVX specification. I'm able to generate SSE1-4.2
fp instructions in AVX form (not all fp instructions are specified yet, but
the plumbing is in place) and am starting on the integer vector instruction
BTW, anyone know why Intel did the most idiotic thing possible and restricted
integer vector instructions to 128 bits? Stupid!
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