[LLVMdev] sign and zero extensions question
eli.friedman at gmail.com
Tue May 26 06:56:36 PDT 2009
On Tue, May 26, 2009 at 6:21 AM, Artur Pietrek <pietreka at gmail.com> wrote:
> Could someone explain to me how the sign/zero extensions in LLVM
> work, please? If I understood correctly, the int type in LLVM doesn't keep
> the information about signedness of an int.
> So the question is how can I
> know if instructions like Load or Trunc should be signed or not?
If you're talking about LLVM IR instructions, neither load nor trunc
does any extension, so it doesn't matter if they are signed or not.
> I guess
> that at least ARM backend produces sign extended load so if someone could
> point me to the code where it happens it would be great (I can't figure it
The code generator combines a sign extension of a load into a
sign-extended load (if you're looking at the code generator, see the
definition of SEXTLOAD in include/llvm/CodeGen/SelectionDAGNodes.h).
There isn't a distinct instruction in the IR.
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