[LLVMdev] difficulting matching i64 subtract immediate due to isel normalization of sub -> add
clattner at apple.com
Mon Jun 29 21:23:43 PDT 2009
On Jun 29, 2009, at 2:52 PM, David Goodwin wrote:
> For some 64-bit immediates, ARM can generate a two instruction
> sequence. For example, for the following code:
> We have code selector patterns for sube and subc that do the right
> thing, but they are not used because isel is converting the "sub i64
> a, i" into "add i64 a, -i". This leads to the attached DAG that is
> impossible to write a pattern for because the addc is producing both
> a carry and a register output, and the adde is consuming the carry
> and producing another output.
> I suppose I can write code to match this... but is there a better way?
You can write a custom expander for legalizetypes of "add i64" that
would handle this case and fall through to the normal legalize code in
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