[LLVMdev] LLVM frontend supporting arbitrary bit-width integral datatypes, semantics extraction

[ihusar]

> Hi Adam,
> any standard compliant C compiler supports i5, believe it or not.
>
> Try this:
>
> #include <stdio.h>
>
> struct i3 { int i:3; };
...
> Ciao,
>
> Duncan.


Hi,

  i knew about this feature and i tried this already, but thank you very much for reminding it to me.
I just needed to make few changes to the generated code and everything works as i expected!
I was doing something wrong before, because the compiler has generated some additional code that would make 
problems when creating instruction selection rules.

If somebody would be having similar problems, I am putting fixed example here:

unsigned int gpregs[32];

struct i16 { int a:16;};

void instr_direct_rri()
{

  int op_arithm_imm = 0x08; {
  int rt = 1; {
  int rs = 28; {
  struct i16 imm16; imm16.a = immread_i16(0); {{ //immread_i16 is a special builtin with return type i16

  int simm = ((int)(imm16.a) << (32 - (16))) >> (32 - (16));

  switch (op_arithm_imm)
  {
     case 0x08:
     case 0x09:
       {if (rt != 0) gpregs[(rt)] = (( (((rs) != 0)?gpregs[(rs)]:0) ) + simm);};
       break;

     case 0x0A:
       {if (rt != 0) gpregs[(rt)] = (( (((rs) != 0)?gpregs[(rs)]:0) ) < simm);};
       break;

  }  

}}}}}

}    

After  clang-cc -O3 -std=c99 tt.c -emit-llvm -o -  I get:


%tmp = tail call i16 @llvm.immread.i16.i32(i32 0) nounwind              ; <i16> [#uses=1]
%conv = sext i16 %tmp to i32            ; <i32> [#uses=1]
%tmp14 = load i32* getelementptr ([32 x i32]* @gpregs, i32 0, i64 28)           ; <i32> [#uses=1]
%add = add i32 %tmp14, %conv            ; <i32> [#uses=1]
store i32 %add, i32* getelementptr ([32 x i32]* @gpregs, i32 0, i64 1)
ret void


that represents exactly what i needed:

set(reg(1), 
  add(
    reg(28), 
    sext(32, imm(0))
  )
)

Thanks a lot
  Adam


On Wed, 24 Jun 2009 15:23:04 +0200, Duncan Sands <baldrick at free.fr> wrote:

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