[LLVMdev] A question about backend implementation of instructions with special register allocation needs.

Gil Dogon gil.dogon at mobileye.com
Mon Jun 22 00:35:57 PDT 2009

I stumbled upon the following problem when truing to support the 
following non-standard  instruction extensions to a MIPS like architecture:

    double store :   Ri,Ri+1  are stored to the memory at address 
specified by (Rj).
    Here the instruction encoding includes only  'i' but it implicitly 
uses also Ri+1.   I can define a special intrinsic for this in "C"
   such as store64(int v1,int v2,int *address), but then I run into 
problems with the register allocation as I need to tell it that
   I want to use Ri and Ri+1 an not just any general pair of registers ....
2.) Just  any kind of instruction with register update semantics. like  
for simplicity sake suppose I have  an instruction such as
      which updates Ri , such as    Ri  <-  somefunc(Ri,Rj).
     can I specify the same argument as both input and output in the 
tablegen instrinfo.td and just hope it works ?

My general question, is if there is some general  way to tell the 
register allocator about constraints when choosing the registers
it allocates because of the requirements of some instructions....

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