[LLVMdev] x86 Intel Syntax and MASM 9.x

[Gaster, Benedict]

Hi Eli,

Thanks for the response I have one question inline.

Regards,

Ben

[...]

> The main problem that I have hit is regarding the use of CL register
in the
> shift instructions. The problem is that ATT syntax states that it
should be
> referenced as "%cl" while Intel says just "cl" but these references
occur in
> X86InstInfo.td and this means that it is shared between Intel and ATT
> printing! For example, the shift rules:

We have two different output styles for precisely that reason.

> The problem is that it does not make sense to have separate rules for
Intel
> and ATT and as such I wanted to get the lists advice on what people
think is
> the best approach to resolving this issue so I can make the changes?

The changes just mentioned looks correct.

[bg]The problem is I am not sure of the best approach to take here. For
example, one possible approach I can see is to following that of the
HasSSE2 constraint and introduce something like the follow to X86.td:

def IsIntelAsmWriter : Predicate<"Subtarget.isFlavorIntel()">; 
def IsATTAsmWriter   : Predicate<"!Subtarget.isFlavorIntel()">;

and then in X86InstrInfo.td make changes something like:

  def SHL8mCLIntel  : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
				   "shl{b}\t{%cl, $dst|$dst, CL}",
				   [(store (shl (loadi8 addr:$dst), CL),
addr:$dst)]>, requires<[IsIntelAsmWriter]>;

  def SHL8mCLATT  : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
				   "shl{b}\t{%cl, $dst|$dst, %CL}",
				   [(store (shl (loadi8 addr:$dst), CL),
addr:$dst)]>, requires<[IsATTAsmWriter]>;

I can get this two work with additional changes to X86InstrInfocpp but
the problem I have with this approach is that it introduces a lot of
duplication, when all I really want to do is parameterize the final
field in the string "shl{b}\t{%cl, $dst|$dst, %CL}". I was wondering
(hoping :-) if you knew of a better method to handling this?

[...]

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